--------------------------------------------------------------------------------
-- Company: 		 U of A
-- Engineer:		 Jesse Xi Chen, ID: 1147349
--
-- Create Date:    00:50:18 10/05/09
-- FILE NAME:		 CA_cell.vhd
-- Design Name:    
-- Module Name:    CA_cell - Behavioral
-- Project Name:   Lab 2
-- Target Device:  
-- Tool versions:  
-- Description: 	 This design file includes the design of a single cell inside
--						 Cellular Automation (CA).
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FSM is
	 -- Inputs : State of the left and right cell,
	 -- 			 A clock signal, an initial value for setting the cell state
	 -- 			 A set_ini actually set the state.
	 -- Outputs: The current state of this cell. 
    Port ( RC_SW, LOS, TIMEOUT, clk, rst: in std_logic;
           state : out std_logic_vector(1 downto 0));

end FSM;

architecture state_machine of FSM is
	-- we implement the CA cell as a finite state machine with
	-- state Dead or Alive.
	type stateType is (Auto_Pilot, Manual_RC, Glide, Forced_Landing);
	signal present_state, next_state: stateType;
	
begin
	comb_logic: process(present_state, RC_SW, LOS, TIMEOUT) is begin
	-- doing to combinational logic according to CA Rule 30
		case present_state is 
			when Auto_Pilot => state <= "00";
				if (LOS = '1') then
					next_state <= Glide;
				else 
					if (RC_SW = '1') then
						next_state <= Manual_RC;
					elsif (RC_SW = '0') then
						next_state <= Auto_Pilot;
					end if;
				end if;
			
			when Manual_RC => state <= "01";
				if (LOS = '1') then
					next_state <= Glide;
				else 
					if (RC_SW = '1') then
						next_state <= Manual_RC;
					elsif (RC_SW = '0') then
						next_state <= Auto_Pilot;
					end if;
				end if;
				
			when Glide => state <= "10";
				if (LOS = '0') then
					next_state <= Manual_RC;
				else 
					if (TIMEOUT = '1') then
						next_state <= Forced_Landing;
					elsif (TIMEOUT = '0') then
						next_state <= Glide;
					end if;
				end if;	
				
			when Forced_Landing => state <= "11";
				if (LOS = '0') then
					next_state <= Manual_RC;
				else 
					next_state <= Forced_Landing;
				end if;		
				
		end case;
	end process comb_logic;

	memory_elements:process(clk, rst) begin
	-- process the memory element for state transition.
		if (rst = '1') then
			present_state <= Manual_RC;
		elsif (clk'event and clk = '1') then
			present_state <= next_state;
		end if;
	end process memory_elements;
end state_machine;