AppNotesVGA

Getting Started with VGA on the Virtex-II Pro Development Board

by Ian Chan and Kevin Au

What you need:

Code from http://embedded.olin.edu/xilinx_docs/projects/bitvga-v2p.php
Xilinx ISE 10.1

Hooking up the board:

USB Platform cable from PC4 JTAG on the Virtex-II to a USB port on a computer.
SVGA from the Virtex-II to an LCD monitor or projector.
Use the JTAG Config (Near the bottom right of the board, there are some switches. Put all three switches in Config Select to off. For Config Source, put switch 1 in the off position and switch 2 in the on position. JTAG Config should be green and Done should be red.
In the System Ace box, a blinking red Error can be ignored.
Hook up the power and turn it on.

Procedure:

Extract the bitvga-v2p.zip file to a folder of your choosing.
Open the Xilinx ISE 10.1. (Project Navigator)
Click File, Open Project and navigate to the folder that you extracted bitvga-v2p to. Open the VGA_demo.ise.
The first thing you see is a prompt to update your code. Don't worry, it works once its updated. The prompt should look like this:

After your project has loaded, which may take some time, it should look like this:

Now we have to configure the connection to the FPGA, because the computer right now does not know where the device we want to program is.

Open the configure target dropdown.
Right-click the Manage Configuration Device.
Select "Open Without Updating".

Once this loads, it asks how you want to tell the navigator where the device is. Since the default is the option we want, (Boundary-scan), click Finish.
A prompt will appear to ask you to assign a configuration file. Click bypass as we will not be using this part of the hardware for this demo.
Click bypass again.

Now we have the option to assign a configuration file for a device we will use. Select main.bit, and click open.

A prompt will appear to allow you to select other files to go along with this configuration file, but it doesn't matter for this. Click OK.

Now we have the chance to set some options, which we don't care about. Click OK.

Now we want to recompile a new configuration file.

Click processes (outlined in red.)
Double-click Generate Programming File (outlined in blue.) This step takes a LONG time. Roughly 10-20 minutes on the lab machines. Go get a drink.
Then click Boundary Scan (outlined in green.) This ensures we are in the right screen to program the device (finally.)

Right-click xc2vp30, and click Program.

Finally, a prompt appears to inform you that the configuration file has been edited, and that you may wants to reload it. (Modified in ISE is outside of iMPACT...) Click Yes.

Now you should have the VGA demo displaying on your LCD screen or projector.

General Overview

There are 4 major modules, included in the MAIN.v verilog file: CLOCK_GEN, SVGA_TIMING_GENERATION, COLOR_BARS, VIDEO_OUT.

Clock_gen creates the pixel clock based on the system clock, and created a buffered systemclock so everything knows how quickly the system is going.
-A pixel clock is also referred to as a dot clock. This determines how often a pixel or a dot is drawn on a screen.
SVGA_TIMING_GENERATION instructs the VIDEO_OUT module how to synchronize the colour data it is getting. Essentially, it tells the VIDEO_OUT how big of a screen to draw.
COLOR_BARS is the module created for the purpose of drawing the coloured bars for the video by the creators of this demo. It feeds the colour for a pixel it wants (8-bits for each colour) into video ram (seperated into three parts, red, green and blue). The video ram stores the 3 bytes of colour at an address based on position, so that each pixel has 3 bytes of ram for its colour.
The VIDEO_OUT module basically takes that colour data from the VIDEO_RAM whenever it needs to draw another pixel, which is regulated by the pixel clock.

Our code, which is included below, switched out COLOR_BARS for a SCREEN_BUFFER module, that creates a 2D array (for each of the three colours). Rather than drawing the colour based on position, like in COLOR_BARS, it stores the screen we want drawn into a screen buffer (the 2D array), and then generates the pixel colour based on the pixel position when it is needed.

Other Information:

Link to our code: Download

Mapping of the VGA code

video_out draws one pixel
color_bars is the screen buffer and it is what outputs the pixels to be drawn
video_out knows the position of the pixel based on the timing/order of the received pixels.
SVGA and clock_gen handle the timing.
A pixel is drawn on every pixel clock by changing vga_red_data, vga_blue_data, and vga_green_data.
The reset goes back to the initial start state.
Make three 2d arrays of red, green, and blue and use that to color.

For reading and writing from these 2D arrays, see Verilog Notes.

Verilog Notes:

2D arrays are declared in the following way:

reg [x:0] varName [y:0]

Accessing 2D arrays must be done in the following way:

reg [x:0] arrayAccessor
arrayAccessor = varName[y]
arrayAccessor = varName[y-1]
...
arrayAccessor = varName[0]